Electrical communication architectures struggle to balance the dichotomy for increased performance required of electronic systems while addressing lower power consumption, smaller form factor, and lower electromagnetic emissions. Better solutions dealing with address scalability while reducing power consumption in computer systems are desirable. A memory system is an example of a typical computer system in which such better solutions are desirable.
The increasing speed of microprocessors requires a corresponding increase in memory bandwidth. The ability to increase available memory bandwidth is constrained by two factors; the number of signal pins available on the processor package; and the speed at which these pins can be driven. The number of available pins is not increasing substantially as this increases both the cost of the package, and the power consumption of the processor. Increasing the per pin speed also increases power consumption.
At the same time the signal integrity problems of high speed electrical signaling mean that less memory devices can be put onto a memory bus as its speed increases. For example, DDR2 and DDR3 memory systems make use of a return data strobe, in order to accurately sample the data being returned from the memory at high speed. However as previously noted, increasing speed reduces the number of memory devices that can be put on the same bus, to the extent that at the maximum DDR3 data rate, only a single memory DIMM is supported. FBDIMM memory systems allow a higher data rate per pin, by using an architecture based on point to point links. Because data and commands have to be forwarded between multiple point to point links, the latency of memory operations grows as more DIMMs are added to the memory system. Additional power is consumed since commands and data have to be retransmitted across multiple point to point hops.
Optical interconnects are available to be used as alternatives to electrical interconnects. Other proposed optical interconnects are between processor and memory in point-to-point configurations. In this arrangement, each channel commonly carries its own timing information by using encoding schemes that insure a high rate of transitions. However, this architecture does not scale well. For example in a memory sub-system with point-to-point connections, the number of transceivers and associated power dissipation would increase due to the increased number of optical interconnects needed to connect all the components.
A low power optical bus providing communication between computer system components which provides high bandwidth access to multiple memory devices is desired.